Cadence Design Systems has announced a landmark partnership with Taiwan Semiconductor Manufacturing Company (TSMC) to co-develop AI-driven chip design automation and intellectual property (IP) solutions for advanced process nodes, including N2, N3P, and A16. The collaboration aims to accelerate semiconductor development for artificial intelligence (AI) and high-performance computing (HPC) workloads, ushering in faster and more energy-efficient chips.
Through this partnership, Cadence’s AI design flow now supports TSMC’s most advanced technologies, while new silicon-proven IP is available for the N3P process. The companies will also collaborate on EDA (Electronic Design Automation) flow development for the upcoming A14 process, expected to debut its first Process Design Kit (PDK) later this year.
“Cadence and TSMC remain committed to helping customers achieve better power, performance, and area outcomes at record speed,” said Chin-Chi Teng, Senior Vice President and General Manager at Cadence. “Our partnership strengthens the global semiconductor supply chain and ensures faster design cycles for AI-driven innovations.”
AI-Driven Design and Automation for Next-Generation Chips
The collaboration builds on Cadence’s growing suite of AI-enabled tools, including the Innovus Implementation System, Tempus Timing Solution, and Voltus Power Integrity Solution, which allow semiconductor designers to optimise power and performance at scale.
TSMC has validated Cadence’s JedAI and Cerebrus solutions, which use AI-assisted automation to detect design rule violations and self-correct them, dramatically shortening design closure times for next-generation chips. These tools are designed to handle the complexity of 3D-IC architectures, enabling more efficient stacking of multiple chiplets and improving data throughput for AI workloads.
“Our collaboration with Cadence is helping us push the boundaries of process innovation and automation,” said Aveek Sarkar, Director of Ecosystem and Alliance Management at TSMC. “Together, we’re addressing the toughest challenges in semiconductor design — performance scaling, energy efficiency, and yield predictability — all essential for the AI era.”
Driving AI Infrastructure and 3D-IC Packaging
The partnership also extends to 3D-IC packaging technologies through TSMC’s 3DFabric platform, which combines advanced packaging and system integration for high-density, multi-die architectures.
Cadence’s 3D-IC tools now include automation capabilities for bump connection management, multi-chiplet alignment, and smart marker insertion, enabling faster development of AI infrastructure chips used in data centers, cloud computing, and autonomous systems.
On the IP side, Cadence introduced several next-generation memory and connectivity solutions built on TSMC’s N3P process — including HBM4, LPDDR6/5X, PCIe 7.0, DDR5 MRDIMM Gen2, and UCIe 32G. These components are key to overcoming the memory-wall challenge that limits AI compute scalability.
Strengthening the Semiconductor Ecosystem for the AI Era
As global demand for AI hardware surges, this collaboration strengthens TSMC and Cadence’s positions as critical enablers of the semiconductor supply chain. Their joint advancements in EDA tools and IP development aim to shorten time-to-market for AI processors, while improving design quality and manufacturability.
By aligning design automation with TSMC’s most advanced nodes, Cadence is helping chipmakers across the world meet the rising demands of AI model training, autonomous computing, and next-gen networking.
