Union Electronics and IT Minister Ashwini Vaishnaw announced India’s roadmap for domestically designed and manufactured 3nm chips by 2032 during a meeting with 24 approved semiconductor design firms under the Design Linked Incentive (DLI) scheme.
Minister Vaishnaw projected that nearly 50 percent of global semiconductor design work could originate from India within coming years, powering smartphones, defense systems, space technologies, and computing infrastructure. The government plans Semicon 2.0 with DLI 2.0 emphasizing fabless startups across compute, RF, networking, power, sensor, and memory categories—representing 75 percent of technology product applications.
DLI Scheme Accelerates Fabless Semiconductor Ecosystem
Minister Vaishnaw met design companies and startups greenlit under flagship DLI, gathering feedback for phase two while outlining tapeout infrastructure: SCL Mohali for 180nm processes and Dholera fab for sub-28nm nodes. Semicon 2.0 prioritizes incentives for six critical chip categories dominating modern applications, positioning India to control design IP for most consumer electronics and strategic systems.
The minister urged individual engineers at global firms to launch fabless ventures, fostering entrepreneurship that retains domestic intellectual property ownership. This human capital strategy transforms expatriate expertise into national capability.
Strategic Roadmap Spans Design to Manufacturing Independence
India’s semiconductor ambition progresses from current 28nm+ capabilities toward cutting-edge 3nm fabrication within six years, aligning with global leaders operating at similar nodes. Minister Vaishnaw envisions 50 fabless companies emerging through next mission phase, capturing high-margin design value while building foundry partnerships for volume production.
Government support includes tapeout facilities, fiscal incentives, and academia-industry collaboration generating novel architectures for domestic needs. By 2029, India expects comprehensive capabilities covering 70-75 percent of application-specific requirements across consumer and strategic sectors.
Fabless Focus Catalyzes IP Ownership Revolution
Minister emphasized individual semiconductor professionals transitioning from global employment to entrepreneurial ventures owning cutting-edge IP—a cultural shift elevating India from services provider to technology originator. Six priority categories represent strategic chokepoints controlling device performance, connectivity, efficiency, sensing, storage, and computation across entire technology stack.
DLI 2.0 establishes clear implementation pathways with defined roadmaps, manufacturing infrastructure, and market development support essential for commercial viability. Feedback integration from phase one recipients ensures iteration based on real-world deployment experience.
Global Competitiveness Through Vertical Integration
2032 timeline positions India among select nations mastering advanced nodes powering AI accelerators, 5G infrastructure, defense electronics, and space payloads. Fabless model maximizes capital efficiency while building ecosystem spanning EDA tools, foundry partnerships, assembly-test-markets, and system integration. Minister Vaishnaw’s vision transforms India from import-dependent consumer to self-reliant producer controlling strategic technology foundations. Semicon 2.0 realizes Atmanirbhar Bharat through targeted incentives creating sustainable competitive advantages across global supply chains.
